1. Field of the Invention
The present invention relates to logic devices, e.g., application-specific integrated circuits (ASICs), programmable logic devices (PLDs), and field-programmable gate arrays (FPGAs), and to computer-aided design (CAD) tools used in the production of such logic devices.
2. Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention(s). Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art.
An asynchronous (also often referred to as an event-driven and/or self-timed) circuit is a circuit that operates without the coordination of one or more globally distributed periodic timing signals called clocks. In contrast, operation of a synchronous circuit is sequenced based on a global clock. Although asynchronous circuits might offer certain advantages over their synchronous counterparts, such as relatively low power consumption, robustness with respect to environmental variations, no clock-skew issues, relatively low electromagnetic interference, and convenient modularity, asynchronous circuits often impose additional operational constraints. For example, it is typically required that an asynchronous logic circuit be glitch-free because of possible malfunctions due to the treatment of glitches as real changes in value.
In general, a digital output signal in a logic circuit might either remain unchanged or change as a result of a circuit action or event. In both situations, the signal might contain a glitch, i.e., one or more reverberations between two digital levels that occur in response to a change in the logic input configuration before the signal finally settles at a corresponding logic level. For example, if the initial and final levels are different and the transition between those levels is not monotonic, then it is said that the signal has a dynamic glitch. On the other hand, if the initial and final levels are supposed to be the same, but the signal still reverberates between two digital levels before settling back to the original (unchanged) level, then it is said that the signal has a static glitch. An asynchronous logic circuit that can potentially produce an unwanted glitch in its output signal is said to contain a hazard. Hence, having a CAD design tool capable of producing hazard-free asynchronous logic circuits is very desirable.